The present invention relates to an improved ethernet card for data transmission between a host computer and an ethernet. The improvement includes a transmitting circuit and a detection circuit. Through the detection circuit, the CPU of the ethernet card detects packet data received by a MAC (media access control), so that packet data is directly discarded or replied to by the CPU if it has nothing to do with the host computer. An arbitration circuit is further added to the ethernet card to arbitrate packet data transmission order when the host computer and the CPU send respective packet data to the ethernet through the MAC and the transmitting circuit respectively at the same time.
The transmission speed of data in computer networks has become more and more faster. In an ethernet, packet data transmission capacity can be as high as 148,800 packets per second (Gigabit ethernet can be faster). Therefore, it is important to improve packet data processing efficiency when designing an ethernet card.
A conventional ethernet card 1, as shown in FIG. 1, generally comprises a CPU (central processing unit) 11, a MAC (media access control) 12, a ROM (read only memory) 13, a transceiver 14, a buffer RAM (random access memory) 15, and a bus 16. The CPU 11 controls the operation of the parts of the ethernet card 1, and runs a related network program stored in the ROM 13. When receiving and transmitting packet data, packet data is received from the ethernet by the transceiver 14, and then received from the transceiver 14 by a receiving circuit 121 of the MAC 12, and then registered in the buffer RAM 15. After inspection by the CPU 11, the CPU 11 informs the host computer 2 to read packet data from the buffer RAM 15. Packet data from the host computer 2 is sent to the buffer RAM 15 through the bus 16, and then transmitted by a transmitting circuit 122 of the MAC 12 to the ethernet through the transceiver 14. As indicated above, either in the receiving mode or the transmitting mode, packet data is registered in the buffer RAM 15 for inspection by the CPU 11, and the MAC 12 is driven to access packet data in the buffer RAM 15 after inspection. Through the bus 16, the host computer 2 reads in packet data from the buffer RAM 15 or writes packet data in the buffer RAM 15. Because the buffer RAM 15 in the ethernet card 1 is commonly used by the CPU 11 and the MAC 12, it must be divided into different memory zones for different purposes, as shown in FIG. 2, and the memory zones must be controlled through a complicated memory management procedure so that packet data can be smoothly received or dispatched.
In order to improve the transmission efficiency of an ethernet card, a complicated arbitration circuit may be installed to arbitrate the time sequence of the common use of the buffer RAM 15 by the host computer 2, the CPU 11 and the MAC 12. The installation of this arbitration circuit greatly increases the cost of the ethernet. This method does not eliminate the complicated problem of the management of the buffer RAM 15.